The CPU, Von Neumann architecture and the FDE cycle - Cambridge IGCSE Computer Science (Paper 1) Exam Questions

Practise 36 exam-style questions on The CPU, Von Neumann architecture and the FDE cycle for Cambridge IGCSE Computer Science (Paper 1). Write your answer as you would in the exam and get it marked in seconds against the mark scheme, point by point, with an AI tutor on hand if you get stuck.

36 questions
1–6 marks each
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20 questions, marked as you go

Sample questions with model answers

Here are 4 of the questions in this topic, each with a model answer, an explanation of why it earns the marks and the mark scheme an examiner would use.

Question 1

1 mark

State the name of the unit in the CPU that decodes instructions and sends out control signals to the other components.

Model answer

The control unit (CU).

Explanation

The control unit decodes the instruction in the CIR and then sends control signals, along the control bus, to make the other components carry it out. The control bus is the connection the signals travel along, not the unit that produces them.

Mark scheme

1 mark
Control unit / CU
do not accept 'control bus' or 'ALU'

Question 2

2 marks

Describe what is meant by Von Neumann architecture.

Model answer

Von Neumann architecture is a computer design in which the program instructions and the data are stored together in the same main memory. The CPU fetches and executes the instructions one at a time using the fetch-decode-execute cycle.

Explanation

The defining idea is the stored program: instructions and data sit in the same memory and are fetched along the same buses. Simply listing CPU components without describing how they work together is unlikely to earn both marks.

Mark scheme

1 mark
Data and instructions are stored together in the same memory
max 2
1 mark
Programs / instructions are stored in memory while they are running (the stored program concept)
1 mark
Instructions are fetched and executed one at a time / in sequence (using the FDE cycle)
1 mark
A CPU uses registers (PC, MAR, MDR, CIR, ACC) and buses (address, data, control) to access memory
1 mark
Data and instructions share the same buses

Question 3

3 marks

Describe what happens during the execute stage of the fetch-decode-execute (FDE) cycle.

Model answer

The control unit sends control signals to the components that are needed to carry out the decoded instruction. If the instruction needs data from memory, its address is placed in the MAR and the data is fetched into the MDR. Any calculation or comparison is carried out by the ALU and the result is stored in the accumulator. The cycle then repeats, fetching the next instruction from the address in the PC.

Explanation

Execution is driven by the control unit's signals; what actually happens depends on the instruction (a calculation in the ALU, a memory read or write, or a jump). Name the components that take part rather than just saying 'the instruction is carried out'.

Mark scheme

1 mark
The control unit sends control signals to the components needed to carry out the instruction
max 3
1 mark
The (decoded) instruction is carried out
1 mark
Any calculation / logic operation is carried out by the ALU
1 mark
The result is stored in the accumulator (ACC)
1 mark
If data is needed from memory, its address is placed in the MAR and the data is fetched along the data bus into the MDR
1 mark
Data may be written to memory (from the MDR along the data bus)
1 mark
A jump instruction changes the address in the PC
1 mark
The cycle then repeats with the next instruction (at the address in the PC)

Question 4

4 marks

The diagram shows a CPU that has just fetched the instruction LOAD 0110 into the CIR, and part of main memory. This instruction copies the data stored at memory address 0110 into the accumulator (ACC).

Give the contents of the MAR, the MDR and the ACC after the instruction has been executed, and name the bus that carries the data from memory to the CPU.

Diagram of the Von Neumann model of a computer system. On the left is a large box labelled "CPU" containing seven boxes in three rows: top row, left to right: PC, CIR and MAR; middle row, left to right: ALU, ACC and MDR; bottom row: a wide box labelled CU. The PC box shows the value 0011; the CIR box shows the value LOAD 0110; the MAR box has an empty value box; the ACC box has an empty value box; the MDR box has an empty value box. On the right is a box labelled "RAM" containing a table with the columns "Address" and "Contents": 0010, LOAD 0110; 0011, STORE 0111; 0100, 0000 0000; 0101, 1110 0010; 0110, 0001 0111; 0111, 0000 0000. Three buses (horizontal lines) join the CPU to the memory: top: a line labelled "Address bus" runs from the MAR box to the memory box, with an arrowhead only at the memory end (one-way, from the CPU to the memory); middle: a line labelled "Data bus" runs from the MDR box to the memory box, with an arrowhead at each end (two-way); bottom: a line labelled "Control bus" runs from the CU box to the memory box, with an arrowhead at each end (two-way).

Model answer

MAR: 0110
MDR: 0001 0111
ACC: 0001 0111
The data travels along the data bus.

Explanation

To execute the instruction, the address 0110 is placed in the MAR and sent along the address bus. The contents of location 0110 (0001 0111) come back along the data bus into the MDR and are then copied into the ACC. A common mistake is to copy the address 0110 into the ACC instead of the data stored there.

Mark scheme

1 mark
MAR: 0110
1 mark
MDR: 0001 0111
accept with or without spaces
1 mark
ACC: 0001 0111
accept with or without spaces
1 mark
Data bus

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